| 摘要 |
The Intelligent DMA Controller (IDMAC) significantly reduces system latency by replacing one or more layers of software with hardware. The IDMAC uses controlwise and datawise intelligence. The controlwise intelligence of the IDMAC is given specific knowledge of the structure of certain pieces of memory or hardware registers, (e.g. parameter blocks), used for Inter Process Communication. This specific knowledge can be imparted during the design phase of the IDMAC, or dynamically provided during its operation as system requirements dictate. The IDMAC achieves its DMA controlwise intelligence by understanding parameter blocks (PBs). The IDMAC reads the structure of the PB from memory directly, gets all of its PB parameters directly from memory, dereferencing as required, and then begins transferring data between the source and destination as instructed by the PB(s). Examples of PB parameters are source address, destination address, transfer length, and data intelligence opcode. The IDMAC allows for bidirectional nesting of PBs, thereby allowing for complete error recovery. Additionally, the IDMAC provides datawise intelligence to effect manipulations on the data that is undergoing a DMA transfer.
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