发明名称 |
Cache memories using DRAM cells with high-speed data path |
摘要 |
A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and data input/output connections are distributed around the memory to increase speed. Multiplexed latch circuitry is provided which incorporates separate data paths for both data read and write operations.
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申请公布号 |
US6201740(B1) |
申请公布日期 |
2001.03.13 |
申请号 |
US19990291536 |
申请日期 |
1999.04.14 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
SEYYEDY MIRMAJID;ZAGAR PAUL S. |
分类号 |
G11C7/10;G11C7/18;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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