| 摘要 |
<p>A delay circuit having: a first delay inverter having complementarily-connected first p-channel FET and first n-channel FET, one of the first p-channel and first n-channel FETs being provided with a gate length elongated; a second delay inverter having complementarily-connected second p-channel FET and second n-channel FET, one of the second p-channel and second n-channel FETs being provided with a gate length elongated; a NAND gate having a first input to which the input signal is applied and a second input to which the output signal of the second delay inverter is applied; and an inverter to output inverting the output signal of the NAND gate.</p> |
