发明名称 |
PARALLEL PROCESSOR ARCHITECTURE |
摘要 |
A parallel hardware-based multithreaded processor is described. The processo r includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory referenc es are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write reference.
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申请公布号 |
CA2391833(A1) |
申请公布日期 |
2001.03.08 |
申请号 |
CA20002391833 |
申请日期 |
2000.08.15 |
申请人 |
INTEL CORPORATION |
发明人 |
WOLRICH, GILBERT;WHEELER, WILLIAM;ADILETTA, MATTHEW J. |
分类号 |
G06F9/30;G06F9/38;G06F15/80;(IPC1-7):G06F15/78 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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