| 摘要 |
PURPOSE: A clock skew minimizing device is provided to construct a clock tree, to analyze the constructed clock tree, and to program a clock skew so that it can minimize the clock skew in the case of designing a synchronization chip driven in synchronization with the clock or embedding a plurality of macro blocks. CONSTITUTION: The device comprises a clock source, the first clock tree, the second clock tree, the first delay compensation module, the second delay compensation module, and the three delay compensation module. The clock source generates clock signals. The first clock tree, installed between the clock source and a control block, delays the clock signals by an arbitrary time, and outputs the delayed clock signals to a plurality of latches of the control block. The second clock tree, installed between the clock source and a macro block, delays the clock signals by an arbitrary time, and outputs the delayed clock signals to a plurality of macros of the control block. The first delay compensation module, installed between the clock source and the first clock tree, compensates for the delays of the clock signals transmitted to the control block in response to overall clock skew. The second delay compensation module, installed between the clock source and the second clock tree, compensates for the delays of the clock signals transmitted to the macro block in response to overall clock skew. The third delay compensation module, installed at clock input ends of the macros, compensates for the delay caused in the second clock and by inner delay of the macros. |
