| 摘要 |
PURPOSE: CMOS voltage level shift circuit is provided to reduce a power and a chip area by using a pull-up transistor and a pull-down transistor when an output node is abruptly pulled up or down. CONSTITUTION: CMOS level shift circuit includes a level shift circuit(40) for outputting a pull-up signal and a pull-down signal after receiving an input signal, and a correction edge detection circuit(50) for generating a pull-up edge detection signal and a pull-down detection signal at the same time. The level shift circuit(40) includes a first transistor(41) having two PMOS transistors, a second transistor(42) having two NMOS transistors, a third transistor(43) having two PMOS transistors and a fourth transistor(44) having two NMOS transistors. PMOS transistors of the first transistor(41) receive an input signal at gate terminals, commonly connect source terminals to a ground terminal, and commonly connect drain terminals to an output terminal. NMOS transistors of the second transistor(42) commonly connect drain terminals to an output terminal, and commonly connect source terminals to a power voltage. PMOS transistors of the third transistor(43) receive an inverted signal at gate terminals, commonly connect source terminals to a ground terminal, and commonly connect drain terminals to an output terminal. NMOS transistors of the fourth transistor(44) commonly connect drain terminals to an output terminal, and commonly connect source terminals to a power voltage.
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