Method and apparatus for facilitating an interface to a digital signal processor

摘要

According to the teachings of the present invention, a data path interface (16) for receiving an incoming signal (14) and facilitating an interface to a digital signal processor (18) includes a synchronizer (62) for determining a signaling frame in a processed signal received from the digital signal processor (18). The data path interface (16) also includes an idle code detector (76) operable to detect an idle code in the incoming signal (14) by comparing the incoming signal (14) to at least one user-programmable idle code pattern. The data path interface (16) further including a least significant bit detector (78) operable to detect a loss of information in the incoming signal (14) by monitoring the status of the least significant bit of each channel to determine whether that bit is stuck at a particular value. The data path interface (16) still further including a daughter card interface (80) operable to receive signals containing eight-bit words and to concatenate those signals to form signals containing sixteen-bit words. The daughter card interface (80) being further operable to transmit the concatenated signal to a daughter card (28).