| 摘要 |
A logic cell for a programmable logic device that features a random access memory adapted to selectively function as additional logic functions for the logic cell or one of a several different types of random access memory. For example, the random access memory may be configured to provide AND-OR logic functions or as a 32x1 single input port random access memory, two 16x1 single input port random access memories or a 32x1 dual input port memory.
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