| 摘要 |
An output MUX for a high speed memory is provided with an interlock circuit to insure that only one data bit can be on the output line at a given time. A plurality of data lines are switched, one at a time, onto a single output line by switching transistors in response to one of a plurality of control inputs. A pair of cross-coupled NAND gates are connected to the output line to produce an LOCK signal whenever data is detected on the output line. The LOCK signal is logically NANDed with each of the control inputs prior to reaching the switching transistors. In this manner, the control signals are effectively locked out and not allowed to propagate through to the switching transistors while the output line is already being driven by data. As long as the LOCK signal remains active any of the control inputs may switch without causing any glitches or fails on the output line. When the active data line becomes inactive, a logic gate resets the pair of cross coupled NAND gates and disarms the LOCK signal in preparation for the next memory cycle MUXing. Thus, the window in which a control signal may transition is considerably broadened by the elimination of one of the timing prerequisites of the MUX control signals. As a result, these control signals may transition anytime prior to the array data for the fastest subarray and thus eliminate cycle time dependencies.
|
