发明名称 TIME ADJUSTMENT SYSTEM OF PLURALITY OF CLOCK
摘要 <p>PROBLEM TO BE SOLVED: To eliminate indication shifting between a plurality of clocks by simultaneously conducting time adjustment of a plurality of clocks with a simple constitution. SOLUTION: Clock 1, clock 2, clock 3,..., clock N are clocks having independent constitutions. The clock 1 consists of an integrated circuit 1 for clock, an indicator 2, a reset switch connected to the reset terminal t1 of the integrated circuit 1 for clock, and a transistor 4 connected between the lines connecting the transistor driving terminal t2 of the integrated circuit 1 for clock to the reset switch 3. The clocks 2 to N are all independent clocks not having the reset switch 3 and the transistor 4 and are provided with integrated circuits 1' for clock having reset terminals t1', indicators 2' and reset lines 6. The above clock adjustment circuit in the clocks 1 to N are connected with a line 5 in series via terminals p1 of each clock.</p>
申请公布号 JP2001059882(A) 申请公布日期 2001.03.06
申请号 JP19990237308 申请日期 1999.08.24
申请人 FUJI HEAVY IND LTD 发明人 AMAGASA YOSHINORI
分类号 G04G7/00;G04G5/00;G04R20/02;(IPC1-7):G04G7/00 主分类号 G04G7/00
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