| 摘要 |
PROBLEM TO BE SOLVED: To reduce leakage currents in a MOS transistor, while the generation of a punch-through in the P-N junction part formed in a triple well at the measurement of a stand-by current is prevented in a semiconductor integrated circuit device. SOLUTION: An inverter 1 of a CMOS constitution consists of a transistor 2, which is formed into a triple well and is provided in an N-type well 5 formed in a P-type semiconductor substrate 4, and a transistor 3, which is provided in a P-type well 6 formed in the well 5. The threshold voltage of the transistor 2 is set high, and the threshold voltage of the transistor 3 is set low. At the measurement of a stand-by current, a supply voltage VDD is applied to the well 5 as a well potential and a well potential VSBB=VSS+β(β=1.5 V or thereabouts) is applied to the substrate 4 and the well 6. Thereby, since a voltage which is applied between the P-N junctions in the respective transistors 2 and 3 can be made low, generation of a punch-through in the P-N junction part formed in the triple well at the time of the measurement of the stand-by current is prevented, and a leakage current in the transistors 2 and 3 can also be reduced.
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