| 摘要 |
PROBLEM TO BE SOLVED: To evade a sudden change of frequency of a VCO even when the frequency of a horizontal synchronization signal to be inputted has the sudden change and then a frequency level is lowered down to the prescribed level or less or disappears. SOLUTION: A phase comparator 2 of a PLL(phase-locked loop) circuit inputs an Hin (horizontal synchronous input) signal via a delay circuit 1 and the RET (feedback) signal of a frequency divider circuit 6 via a delay circuit 7 respectively to carry out phase comparison of both signals. An AFC(automatic frequency control) filter 4 is connected to a switch 3 which flows a phase error current to connect its output to an output side of the comparator 2 to control voltage of a VCO 5 only in an ON period when the Hin signal is inputted. In such a constitution, no phase error current is flowed not to change the VCO 5 when the Hin signal disappears. The phase error current is made to flow within pulse width of the Hin signal and in time length equivalent to the delay time of the circuit 1 when the Hin signal has high and low frequency levels, respectively. |
