发明名称 |
Double incrementing, low overhead, adder |
摘要 |
A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight ("first weight"). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receive bits of the two input values of a common weight ("second weight") one bit more significant than the first weight. The three input XOR gate is configured to XOR these values with the AND'ed bit to generate a three input XOR'ed bit.
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申请公布号 |
US6199090(B1) |
申请公布日期 |
2001.03.06 |
申请号 |
US19980100499 |
申请日期 |
1998.06.19 |
申请人 |
ATI INTERNATIONAL SRL |
发明人 |
MANSINGH SANJAY;PURCELL STEPHEN CLARK |
分类号 |
G06F7/50;G06F7/506;(IPC1-7):G06F7/50 |
主分类号 |
G06F7/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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