发明名称 Semiconductor memory device with hierarchical bit line architecture
摘要 A semiconductor memory device includes a semiconductor substrate, a plurality of word lines, a plurality of decoders for selectively activating the plurality of word lines in accordance with an address, and a plurality of banks arranged in a predetermined direction. Each of the plurality of banks is connected to at least one of the plurality of word lines. At least two of the plurality of word lines are connected to one common decoder of the plurality of decoders. Each of at least two of the banks is connected to the at least two word lines of the plurality of word lines. The at least two banks are not adjacent.
申请公布号 US6198648(B1) 申请公布日期 2001.03.06
申请号 US19990451190 申请日期 1999.11.29
申请人 SHARP KABUSHIKI KAISHA 发明人 KOMATSU KOJI
分类号 G11C17/18;G11C8/14;G11C16/06;(IPC1-7):G11C5/02 主分类号 G11C17/18
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