| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain an input clock signal of a proper pulse width by resetting a pulse signal generated from a pulse generator by a reset clock signal from a delay stage in the middle of a delay circuit. SOLUTION: When a frequency-demultiplexed clock signal leads clock signal in the phase, variable delay circuit 155 is increased in the delay, and operates so that the phase of the frequency-demultiplexed clock signal coincides with the one of the clock signal. In the case that the frequency-demultiplexed clock signal is delayed from the clock signal, the variable delay circuit 155 is decreased in the delay, and performs similar operation. And when the pase of the frequency-demultiplexed clock signal coincides with the one of the clock signal, a pulse signal CLK-PLS and /CLK-PLS are set at a high level, and then reset at a low level with a quarter period of the clock signal, therefore, an input clock signal CLKIN and an internal clock signal of an approximately 50% duty ratio can be obtained.</p> |
