发明名称 DEVICE AND METHOD FOR DESIGNING TEST PATTERN FOR VERIFICATION
摘要 PROBLEM TO BE SOLVED: To efficiently design and input test patterns for verifying the operation of electronic circuits. SOLUTION: This designing device is provided with an input device 2 to provide an instruction to input a signal to each terminal of electronic circuits, a test pattern creating mean 5 to control test pattern creation according to the input instruction, an arithmetic processing device 3 to perform arithmetic processing for test pattern designing by various commands from the creating means 5, and an output device 1 to display a test pattern input screen in tabular format for inputting test patterns, a mnemonic setting screen to provide mnemonic names for combinations of signals to be frequently used, and a time chart screen for displaying input results in waveform format, which are the results of processing of the arithmetic processing device 3. Test pattern signals are inputted on the screen in tabular format so as to perform designing based on the designing processes of the test patterns, combinations of signals are related with mnemonic names so as to input the combinations of signals to be frequently used in the mnemonic names, and input results are displayed on a screen in waveform format.
申请公布号 JP2001059858(A) 申请公布日期 2001.03.06
申请号 JP19990235402 申请日期 1999.08.23
申请人 NEC COMMUN SYST LTD 发明人 KONDO MASAMITSU;KONDO SHUNSUKE
分类号 G01R31/3183;G06F11/22;G06F17/50 主分类号 G01R31/3183
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