发明名称 Clock slew control for serial communication systems
摘要 A system and method for accounting for clock slew during autobauding. Upon identifying an AT command and the baud rate of the incoming data stream, the present invention accounts for clock slew in one of two ways, depending upon the baud rate of the incoming data stream. If the baud rate of the incoming data stream is 9600 or greater, the present invention accounts for slew by utilizing a feature associated with ASCII characters and RS-232 protocol, that is the stop bit being nicely framed on both sides by spaces. This feature is used to determine whether negative or positive clock slew exists. If negative clock slew exists and it is determined that negative clock slew falls within a certain threshold, a sample is skipped. If positive clock slew exists and falls within a certain threshold, positive clock slew is converted to negative clock slew by taking an extra sample. Clock slew is accounted for by reconstructing bits from an old sample and a new sample, based on the calculated slew value, to obtain an actual sample that eliminates deleterious effects of clock slew. When the baud rate of the incoming data stream is less than 9600, the present invention accounts for clock slew by taking a middle group of 8 samples from the start bit when multiple groups of 8 samples per bit exist. This is accomplished by searching for the next start bit. Once the next start bit is found, determining which group of 8 samples is a middle sample.
申请公布号 AU6523600(A) 申请公布日期 2001.03.05
申请号 AU20000065236 申请日期 2000.08.03
申请人 QUALCOMM INCORPORATED 发明人 JAE NOH
分类号 G06F13/42;H04L7/033;H04L25/02;H04L25/08 主分类号 G06F13/42
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