| 摘要 |
PURPOSE: A clock forwarding circuit having characteristics for detecting an automatic clock delay and setting an initial parameter is provided to transmit data between circuits without error and the affection due to the delay in interface clocks, by automatically detecting the delay, and by forwarding the clocks corresponding to the detected delay. CONSTITUTION: A clock generator(110) produces the bit clock for inputting and outputting data. An output clock control logic(120) controls the clock signal from the clock generator(110) to generate and apply an output clock signal(CLK_OUT) to a slave circuit. The data(DATA_OUT), transmitted from the internal data bus(130) of a master circuit, is output to the slave circuit via a data control logic(170). The slave circuit receives the clock signal(CLK_OUT) and the data(DATA_OUT), and outputs an input clock signal(CLK_IN) and an input data(DATA_IN) to a clock forwarding circuit(100) in the master circuit. A delay detection circuit(180) automatically detects the delay and applies the initial parameter(init_UNLD) corresponding to the delay to a load/unload clock control logic(150). |
