| 摘要 |
PURPOSE: A port circuit is provided to delay one of data signals applied to gates of PMOS/NMOS transistors in rising and falling edges of the data signals, thereby prevent the generation of the short-circuit current due to the simultaneous turn on of the transistors. CONSTITUTION: The port circuit comprises an inverter(I1), a NAND gate(NAND1), a NOR gate(NOR1), delayers(100,110), a PMOS transistor(PM1) a NMOS transistor(NM1). The inverter(I1) inverts a control signal. The NAND gate(NAND1) performs a NAND operation of the control signal and a data signal. The delayer(100) detects a falling edge of the data signal to delay the output signal of the NAND gate. The delayer(110) detects a rising edge of the data signal to delay the output signal of the NOR gate. The transistor(PM1) is conducted by the output signal of the delayer(100) to output a source voltage(VCC) of a source to an output port(PIN) through a drain. The transistor(NM1) is conducted by the output signal of the delayer(110) to output a ground voltage(VSS) of the source to the output port(PIN) through the drain.
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