| 摘要 |
PURPOSE: A circuit arrangement of a dynamic random access memory(DRAM) is provided to easily make an input/output interface and to reduce a chip area when a general synchronous DRAM is used in an embedded DRAM, by piling up a plurality of memory banks in a predetermined direction, and by commonly using a bit line and an input/output sense amp block. CONSTITUTION: A plurality of memory banks(40,42) include bit line sense amplifiers, Y decoders and X decoders(414). The bit line sense amplifiers are located between cell array blocks(412). The Y decoders are located in a lower part of the bit line sense amplifiers and the cell array blocks. The X decoders are located at a side of the cell array blocks. The memory banks are arranged in a predetermined direction. Bit lines are positioned in the predetermined direction through the memory banks, and an input/output sense amp block(44) is positioned at ends of the bit lines.
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