| 摘要 |
A ratio logic gate has a current mirror (20) controlled by the pull-down transistors (10-13) and supplying a half size pull-down transistor (23). When one or more of the input pull-down transistors (10-13) is on, the mirror current overcomes the output pull-down transistor (23) to provide a high potential output. Process tolerances between p and n type devices is thus avoided. <IMAGE> |
