High frequency semiconductor device

摘要

A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or decreased thermal dissipation. In a preferred embodiment, the gate capacitance is reduced over prior art methods and structures by etching to the gate 14 and directly contacting the p+ gate with a p-ohmic contact 24. In another embodiment, the area under the gate contact 22 is implanted with a "trim" dopant, where the trim dopant acts to reduce the doping of the drawing layer thereby reducing the capacitance. In another embodiment, the area under the exposed gate contact 22 is isolated by ion damaged to reduce the doping/conductivity of the n- drain layer below a portion of the gate layer to reduce the gate-to-drain capacitance. <IMAGE>