发明名称 |
Semiconductor device having semiconductor memory circuit to be tested, method of testing semiconductor memory circuit and read circuit for semiconductor memory circuit |
摘要 |
Disclosed herein is a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means to specify defective portions produced in a memory section of the semiconductor memory circuit and shorten the time necessary for its test. The present semiconductor device comprises a test pattern generator for generating a test pattern indicative of the type of test and an expected value estimated to be obtained by the test pattern in response to a command issued from the test means, the semiconductor memory circuit, which has a plurality of memory cells disposed in the form of a matrix with rows and columns and respectively store data therein and is activated based on the test pattern so as to output data in the respective memory cells every columns, a decision unit for comparing each output data with the expected value and outputting the result of comparison therefrom and a translation unit for converting the result of comparison into address data and outputting it to the external test means.
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申请公布号 |
US6195771(B1) |
申请公布日期 |
2001.02.27 |
申请号 |
US19970807462 |
申请日期 |
1997.02.27 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD |
发明人 |
TANABE TETSUYA;TANOI SATORU;TOKUNAGA YASUHIRO |
分类号 |
G01R31/28;G06F12/16;G11C11/401;G11C11/413;G11C29/00;G11C29/14;G11C29/44;G11C29/56;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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