发明名称 Method and apparatus for the functional verification of digital electronic systems
摘要 A method and apparatus capable of generating and executing large numbers of functional tests for complex digital electronic systems at low cost are presented. The apparatus includes a test generator which uses a decision tree representation of a verification space, derived from a functional specification of the digital electronic system, to generate functional tests. A decision tree representation of a verification space includes an initial goal node, a leaf goal node, and at least one intermediate goal node interconnected by a plurality of directed decision arcs formed between the initial goal node and the leaf goal node. Goal plans assigned to goal nodes include operations which generate functional tests. Functional tests are generated by recursively "walking" the decision tree, the choices of which goal node to visit next being made at random and according to decision weights assigned to each goal node. The decision weights assigned to each goal node in the decision tree may be adjusted to ensure all portions of the verification space are adequately tested. A testing system issues functional tests to both a golden device and a device under test. The testing system compares expected responses from the golden unit to responses from device under test and produces functional test results. Specialized structures called monitors ensure sets of functional tests (i.e., functional test suites) exercise all parts of a system implementation.
申请公布号 US6195616(B1) 申请公布日期 2001.02.27
申请号 US19990390826 申请日期 1999.09.07
申请人 ADVANCED MICRO DEVICES, INC. 发明人 REED DAVID F.;HAMID ADNAN A.
分类号 G01R31/3183;(IPC1-7):G01R31/28 主分类号 G01R31/3183
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