发明名称 MULTI-BIT NON-VOLATILE MEMORY UTILIZING NON-CONDUCTIVE CHARGE TRAP GATE
摘要 PROBLEM TO BE SOLVED: To obtain a non-volatile memory which can record multi-level data, has new structure, and is programmable. SOLUTION: This memory is a non-volatile memory having first and second source/drain area SD1, SD2 on the surface of a semiconductor substrate, and a non-conductive trap gate TG and a conductive floating gate CG on a channel area between SD1 and SD2 through an insulating film. This non-volatile memory has a first or a second state in which voltage is applied between the first and second source/drain area SD1, SD2 and hot electrons generated near the first or the second source/drain area are trapped locally by a first or a second trap gate region TSD1, TSD2, and a third state in which voltage is applied between a control gate and the channel area, and electrons (or electric charges) are injected into the whole trap gate TG. Information on one bit is recorded by making the memory into the third state or not, and information on two bits is recorded by making the memory into the first state or the second state or not. Therefore, information on total three bits is recorded in one memory cell.
申请公布号 JP2001057093(A) 申请公布日期 2001.02.27
申请号 JP19990226913 申请日期 1999.08.10
申请人 FUJITSU LTD 发明人 KAWAMURA SHOICHI
分类号 G11C11/56;G11C16/02;G11C16/04;H01L29/788;H01L29/792 主分类号 G11C11/56
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