CLOCK SKEW CORRECTING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a clock skew correcting circuit capable of canceling the jitter of an internal clock signal and simultaneously remarkably reducing power consumption as well by providing a detecting circuit for detecting a change in the polarity of a phase difference, and fixing the value of a control signal by the detecting circuit. SOLUTION: An external clock signal 1 is inputted, delayed just for a prescribed delay quantity as needed and outputted as an internal clock signal 2 by a delay means DR. A comparing and control means CC compares the phase of the external clock signal 1 with that of the internal clock signal 2 and controls the delay quantity of the delay means DR so as to reduce 'deviation' in the phase of the internal clock signal 2 in respect to the phase of the external clock signal 1. A fixing means FC fixes the delay quantity at least once inverting the polarity of 'deviation' in the phase of the internal clock signal 2 in respect to the phase of the external clock signal 1 and cuts off a feedback loop. Thus, the jitter of the internal clock is reduced and power consumption can be reduced.