发明名称 CIRCUIT PATTERN INSPECTING METHOD AND DEVICE TO BE USED THEREFOR
摘要 PROBLEM TO BE SOLVED: To determine the suitability of a circuit pattern by obtaining the amounts of displacement in X- and Y-directions for every location correction area of master image data, shifting the master image data in the X- and Y-directions by the obtained amounts, and comparing it with image data for inspection for every location area. SOLUTION: A line memory+shift register 52 for developing master data develops image data captured by dividing master data for every location correction area into M×N pieces. The developed data is transmitted to a mismatch enumerating circuit 54 to obtain the number of mismatches with defect candidate data, and the obtained number is stored in enumeration result storage memory 56. The location correction value of each location correction area is obtained at an area-by-area location correction value calculating routine 58 and compared with the location correction value of an adjacent location correction area at a location correction modification routine 60, and a location correction value in the closest area is substituted at the time of separation by a predetermined value or more. The master data is shifted in the X- and Y-directions by the location correction value determined for every location correction area and compared with image data for inspection for every location correction area to determine the GO/NO-GO of a circuit pattern.
申请公布号 JP2001056301(A) 申请公布日期 2001.02.27
申请号 JP19990231929 申请日期 1999.08.18
申请人 IBIDEN CO LTD 发明人 WAKINO TOMOO
分类号 H05K3/00;G01N21/956;G01R31/02;(IPC1-7):G01N21/956 主分类号 H05K3/00
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