| 摘要 |
PROBLEM TO BE SOLVED: To shorten a cycle time of a static RAM incorporated in a logic integrated circuit as a macro-cell. SOLUTION: An enable-pulse ENP for making a word line a pulsative operation state during only the prescribed period is generated as a substantial AND signal of an internal clock signal ICLK and an inversion delay signal ICDB by its variable delay circuit VDL, while the device comprises a data comparing circuit making selectively a data coincidence signal DM a valid level when a test result is normal and a counter CTR receiving a valid level of the data coincidence signal DM and counting down it selectively, the device is provided with a pulse width control circuit PWC generating delay control signals DC 0-DCk of (k+1) bits as its output signal, the device has such a constitution that a delay time for an internal clock signal ICLK of the VDL is selectively switched conforming to DC0-DCk, further, a static RAM is provided with a function optimizing autonomously pulse width of the enable-pulse ENP in accordance with operation characteristics of relating circuits. |
