MLSE implementation using a general purpose DSP and shared hardware for a GSM application

摘要

A digital signal processor (DSP), hardware module, and shared memory coupled together to perform Viterbi decoding on a sequence of received symbols. Given channel coefficients, the DSP calculates initial data for Viterbi processing: combination values for each possible state and branch product values for each possible symbol. These values are stored in shared memory for access by the hardware module. The DSP further calculates the first few stages of the Viterbi processing so path metrics are well defined for every state. Path metric values are also stored into the shared memory. The hardware module is optimized to perform calculations associated with a single stage of the Viterbi algorithm. The DSP invokes by the hardware module by passing a received sample to the hardware module. The hardware module calculates a survivor state value and minimizing path metric value for each state in the state space.