发明名称 DEVICE AND METHOD FOR MATHEMATICAL ARITHMETIC CIRCUIT COMPOSITION
摘要 PROBLEM TO BE SOLVED: To automatically put various addition algorithm together by a CTD (counter tree diagram), which can systematically represents arbitrary addition algorithm of a weight number system, according to the equivalent conversion of the CTD. SOLUTION: In a composition process wherein a 4-bit 4-input 2-output adder 800 is quad SD number adders 842, 844, 872, and 874 actualizing a composition target by using a multi-valued integrated circuit, deformation from a figure (a) to a figure (b) is the decomposition of a directed side of a counter node 800. Deformation from (b) to (c) is the serial decomposition of a counter node 810 and the decomposition of a directed side. Deformation from (c) to (d) is the serial decomposition of counter nodes 820 and 830 and part of it is quad SD number adders 842 and 844 as targets. Conversion from (d) to (e) is deformation of quad SD number adders 872 and 874 through the parallel decomposition of counter nodes 850 and 860. Consequently, all are quad SD number adders.
申请公布号 JP2001056826(A) 申请公布日期 2001.02.27
申请号 JP19990231247 申请日期 1999.08.18
申请人 JAPAN SCIENCE & TECHNOLOGY CORP 发明人 AOKI TAKAFUMI;HIGUCHI TATSUO;SAKIYAMA ATSUSHI
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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