BUFFER MEMORY CONTROL SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide a buffer memory control system capable of shortening processing time by receiving an access request without waiting the completion of block transfer processing when the logical address of the next access request and a logical address starting block transfer are in the same block. SOLUTION: An access request is sent from an access request source to a buffer memory control part 1. The logical address arriving through a signal line 1b is transmitted to a signal line 1e and connected to a comparator circuit 15. The logical address under block transfer held in a register BTLAR 8 is connected to the comparator circuit 15 and both block address parts are compared. The buffer memory control part 1 monitors the intra-block address of transferred data, and when the data of the target address arrive and the following access request is the request of access to the same block, even during block transfer, the request can be received/processed without waiting the completion of block transfer.