| 摘要 |
PURPOSE: An on-resistance of a power MOS device is reduced without increasing the channel density below a gate area. CONSTITUTION: The power MOS device has a semiconductor substrate (101) and a first conduction type upper layer (102) provided on the substrate. The upper layer has on its top surface a plurality of well areas (103) of a second conduction type a plurality of heavily doped source areas (104) of a first conductivity type, and a wavy part (202) which is formed by selective etching and parallel to the source areas. A wavy gate area (205) is formed including the wavy part (202) to increase channel width by the well areas (103), source areas (104), and gate area (205). For the manufacture, a striped mask is formed on the top surface (201) of the upper layer and etched to form a wavy top surface having a plurality of parallel wavy parts (203). The striped mask is removed and an insulating film (206) and conductive film (207) are formed on the upper-layer top surface (201) having the wavy surface layer to constitute the wavy gate area (205).
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