| 摘要 |
A data processing machine with nonuniform memory access and cache coherency is constituted by a plurality of modules (10, 20, 40, 60), a given module (10) including a unit (6) to assure data coherence with other modules (20, 40, 60), characterized in that said unit (6) includes at least the following:a first register (81, 101) intended to contain a first physical address of the memory,a second register (82, 102) intended to contain a second physical address of the memory,first means (90, 95, 111, 121, 88, 92, 108) for measuring a quantity of activity relating to the data whose addresses are included between said first physical address and said second physical address,a third register (83, 93, 109) intended to contain a threshold value for measuring said quantity of activity,second means (91, 94, 112, 122) for detecting the exceeding of said threshold value by the quantity of activity measured by the first means. |
