| 摘要 |
PURPOSE: To provide a semiconductor memory which can operate with active width of an appropriate column address selecting signal. CONSTITUTION: This device is constituted so that at the time of a test mode, test mode signals of several kinds are generated, a set signal (e) is delayed by delay quantity of several kinds, thereby, a YSW signal (i) being a column address selecting signal having width of several kinds is generated in a column address decoder circuit 5. And in a memory cell array 6, at the time of a test mode, delivery and receipt operation of data is performed by the YSW signals (i) of several kinds in accordance with a test mode, appropriate YSW signal (i) can be appreciated. Operation is performed by optimum YSW signal (i) at the time of normal operation by switching fuses in a fuse circuit 16 based on an operation result at the time of test mode.
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