发明名称 DATA PROCESSOR AND DIVISION AND REMAINDER ALGORITHM
摘要 PURPOSE: To prevent the generation of the waste of repetition processing when the valid bit width of data to be processed under a division and remainder instruction is small. CONSTITUTION: An instruction decode part 2 inputs and decodes an instruction code having a size field S for storing data size information. Then, the instruction decode part 2 outputs the decoded result to a control part 1. A control logic 22 in the control part 1 sets the number of times of arithmetic processing loop of a division instruction and a remainder instruction based on dividend data size information stored in the size field S of the instruction code. Then, the repetition processing of the division and remainder arithmetic operation is executed only by the set number of times of processing loop by an ALU 811 in an arithmetic part 8.
申请公布号 KR20010014926(A) 申请公布日期 2001.02.26
申请号 KR20000026613 申请日期 2000.05.18
申请人 MITSUBISHI ELECTRIC CORP 发明人 OOTANI SUGAKO;KONDOU HIROIKU
分类号 G06F7/537;G06F7/00;G06F7/52;G06F7/535;G06F9/30;G06F9/302;G06F9/305;G06F9/32;(IPC1-7):G06F7/00 主分类号 G06F7/537
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