| 摘要 |
PURPOSE: A support is provided to overcome the restrictions of the performance of an existent memory system by adjusting a load address buffer, a register file, and a data flow between a 1st and a 2nd data source so that a plurality of load requests can be put in an unprocessed state at the same time. CONSTITUTION: The array of a load buffer has entries (e.g. load address entries) as to five load addresses. The addresses of up to five unprocessed load requests can be stored in those five load addresses. A circuit in the load buffer operates under the control of an LSU controller having different state machines as to the respective entries in the array. In this case, the load address buffer, register files and the data flow between the 1st and 2nd data sources are so controlled as to both the 1st and 2nd data sources so that the plurality of load requests can be put in an unprocessed state at the same time.
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