发明名称 METHOD FOR FORMING VIA FILLED WITH CONDUCTOR AND METHOD FOR MANUFACTURING MULTILAYER WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To provide a multilayer wiring board which is superior in reliability and durability having a wiring layer whose relatively large via hole is completely packed inside with metal, and whose surface is made flat without making thick the wiring layer. SOLUTION: An insulating layer 3 is formed on a base wiring layer 2 on a substrate 1, and a non-electrolytic copper plated coating 4 is formed on the upper face of the insulating layer, and an insulating protecting coating 5 is formed on this coating 4. Then, a via hole 6 is formed, a non-electrolytic copper plated coating 7 is selectively formed at the insulating parts of the via hole side wall parts, and the via hole is packed with copper metal 8 by the first electrolytic copper plating. Afterwards, the insulating protecting coating 5 is removed, and a wiring pattern 10 is formed by electrolytic copper plating by using a plated resist pattern 9 in the same way as a semi-additive method.
申请公布号 JP2001053444(A) 申请公布日期 2001.02.23
申请号 JP19990225232 申请日期 1999.08.09
申请人 SUMITOMO METAL IND LTD 发明人 SHIBUYA MASAYUKI;KISHIMOTO YOSHIHISA
分类号 H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K3/46
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