发明名称 SHIFT REGISTER AND ELECTRONIC EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To shift a signal to a post stage without attenuation a level of the output signal and to suppress the variation of characteristics of a transistor. SOLUTION: When a (k)th stage of this shift register is taken as an example, a TFT 21 is turned on by an output signal OUTk-1 of the (k-1)th stage, and outputs a level of the output signal OUTk-1 to wiring capacitors C2, C5. When the output signal OUTk-1 is the high level, electric charges are accumulated in the wiring capacitors C2, C5, and the TFTs 22, 25 are turned on. The TFT 22 is turned on by power source voltage Vdd supplied through a TFT 23 and a TFT 26 is turned off. When a signal CK1 is made the high level, this signal is outputted as an output signal OUTk through a TFT 25. Also, a TFT 27 is turned on by an output signal OUTk+1 of (k+1)th, and discharges the electric charges accumulated in the wiring capacitors C2, C5. In this case, the TFT 26 is turned on, and constant voltage Vss is outputted as the output signal OUTk.
申请公布号 JP2001052494(A) 申请公布日期 2001.02.23
申请号 JP19990224660 申请日期 1999.08.06
申请人 CASIO COMPUT CO LTD 发明人 KANBARA MINORU
分类号 G11C19/00;G02F1/133;G09G3/20;G09G3/36;G11C19/28 主分类号 G11C19/00
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