| 摘要 |
PROBLEM TO BE SOLVED: To reduce the hardware quantity of a carry storage type partial product adder while suppressing an increase in delay due to the high load capacity of code bits by the code extension of partial products as to a fixed-point multiplier used for a processor, etc. SOLUTION: This multiplier comprises a multiplier decoding circuit 101, a partial product generating circuit 102, a partial product adder 103, a carry storage adder 104, and a carry propagation adder 105. A correction value selector 506 which selects rounding correction value groups selects a correction value for rounding at a desirable digit and a correction value subtracter 507 subtracts a partial product correction value for omitting the code expansion of a partial product from the selection output and supplies it to the carry storage adder 104. |
