发明名称 DETECTING METHOD OF DELAY FAILURE OF LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make detectable even a slight delay of each logic element by using a random-number sequence or using an inspection list which activates routes of a sufficiently small number as compared with the number of all existing routes. SOLUTION: When an inspection list is generated, a delay failure is supported inside a logic circuit to be tested, a first memory element group is shifted to a second internal state from a first internal state, and a signal transition is generated at an output terminal so as to be propagated to a second memory element. Alternatively, a third memory element in which a signal transition is passed through a failure supposition part from the part group of external input terminals so as to reach the input terminal is searched, or a route in which the signal transition is propagated to the part group of the external input terminals is searched. Then, the signal propagation time on the route is calculated, a first parameter value is set so as to be situated between its maximum value and a value in which a first parameter value expressing the degree of the signal propagation delay of a delay failure to be supposed is subtracted from the threshold value corresponding to a test time interval, and a supposed failure can be detected.
申请公布号 JP2001051027(A) 申请公布日期 2001.02.23
申请号 JP19990229973 申请日期 1999.08.16
申请人 HITACHI LTD 发明人 NAGUMO TAKAHARU;HIRANO JUN;NAKAO NORINOBU
分类号 G01R31/28;G06F17/50;(IPC1-7):G01R31/28 主分类号 G01R31/28
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