| 摘要 |
PROBLEM TO BE SOLVED: To provide a 2 transistor 1 capacitor type gain cell having high opera tional reliability and quality in which a capacitor electrode can be formed utilizing a logic interconnection layer. SOLUTION: A memory cell comprises a write transistor, a read transistor TR connected with the feeder line of power supply voltage (drain impurity region 5), and a capacitor CAP connected with the control electrode (gate electrode 3) of the transistor TR. The capacitor CAP has a multilayer structure of a lower electrode 8, a capacitor dielectric film 10, and an upper electrode 11 where the lower electrode 8 serves both as a memory node and the upper electrode 11 as a word line (read word line). The lower electrode 8 has an inclining side face and a triangular (or trapezoidal) cross section. The upper electrode 11 covers to shield the lower electrode 8 serving as a memory node. |
