发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a technique for attaining a dual-damascene wiring in the desired shape and also suppressing increase of the inter-wiring capacitance. SOLUTION: Increase in inter-wiring capacitance can be suppressed by setting to about 50 nm the thickness of a silicon nitride film 6 provided as an etching stopper layer between an upper layer wiring M2 and a lower layer wiring M1. Moreover, the desired etching shape can be attained by providing, as the upper layer of the silicon nitride film 6, a first TEOS oxide film 7, having higher etching selection ratio for the silicon nitride film 6 so that the silicon nitride film 6 functions effectively as the etching stopper layer.
申请公布号 JP2001053151(A) 申请公布日期 2001.02.23
申请号 JP19990230423 申请日期 1999.08.17
申请人 HITACHI LTD 发明人 AOKI HIDEO
分类号 H01L23/522;H01L21/3205;H01L21/768;(IPC1-7):H01L21/768;H01L21/320 主分类号 H01L23/522
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