| 摘要 |
PROBLEM TO BE SOLVED: To shorten access time while reducing power consumption of a static RAM having a CMOS circuit as a basic element. SOLUTION: A semiconductor integrated circuit device comprises a static RAM, having a memory array MARY0 of CMOS memory cells MC arranged in lattice as a basic compositional element, where the non-inverted signal line B0T and inverted signal line B0B of complementary bit lines are precharged to high level at nonselection, the basic device structure is an SOI structure and a P-type well region for forming the N-channel MOSFETR N1-N4 of a memory cell MC in the memory array MARY0 is formed independently in units of sub-word line. The P-type well region is applied with an well voltage of first relatively low potential, e.g. a ground potential VSS, when a corresponding sub-word line SW0 is in a nonselection state and applied with an well voltage of second relatively low potential, when it is in selection state. |
