发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To prevent generation of nonconformity of an irregularity in the threshold voltages of MISFETs within the surface of a wafer in a semiconductor device of a structure, wherein element isolation grooves are formed in the wafer using a chemical and mechanical polishing method. SOLUTION: Element isolation grooves 5 are formed in a wafer 1, using a chemical and mechanical polishing method, and thereafter impurities for adjusting the threshold voltages of MISFETs are introduced in the wafer 1. After that, impurities for adjusting the threshold voltages are introduced once more in the vicinity, where lack in does of the impurities of the outer peripheral part of the wafer 1, whereby the difference between the threshold voltages of the MISFET, which is formed in the vicinity of the outer peripheral part of the wafer 1, and the threshold voltage of the MISFET, which is formed in the central part of the wafer 1, is dissolved.
申请公布号 JP2001053240(A) 申请公布日期 2001.02.23
申请号 JP19990229654 申请日期 1999.08.16
申请人 HITACHI LTD 发明人 ASAKURA HISAO;TADAKI YOSHITAKA;OYU SHIZUNORI;SEKIGUCHI TOSHIHIRO
分类号 H01L21/76;H01L21/304;H01L21/8242;H01L27/08;H01L27/108 主分类号 H01L21/76
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