发明名称 LOW-CLOCK FEEDTHROUGH CHARGE PUMP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To stabilize the frequency of the output signal of a phase-locked loop(PLL) by providing a charge pump circuit which reduces the jitter by reducing a charge injection phenomenon. SOLUTION: This circuit is equipped with 1st and 2nd pump transistors C1 and C2, 1st to 4th switching means 22a to 22d, and 1st and 2nd wide swing current mirrors 19a and 19b. Then the 1st and 2nd wide swing current mirrors 19a and 19b are composed of cascade transistors and bias circuits and provide bias needed for the charge pump circuit, and the 1st to 4th switching means 22a to 22d and cascade transistors include transistors which operate in saturation areas, so a charge injection phenomenon is reduced to reduce jitter.
申请公布号 JP2001053604(A) 申请公布日期 2001.02.23
申请号 JP19990323428 申请日期 1999.11.12
申请人 ISEI DENSHI KOFUN YUGENKOSHI 发明人 RIN SHIHO;KYO TENSHO
分类号 H03L7/093;H03L7/089 主分类号 H03L7/093
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