PHASE-LOCKED LOOP OSCILLATION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To shorten a lock time without spoiling the stable operation of a PLL circuit. SOLUTION: The PLL circuit 11 has a 1st digital phase comparator 13 and a 2nd digital phase comparator 15 which has a wider dead zone than it. Error signals outputted from the 1st phase comparator 13 and 2nd digital phase comparator 15 are outputted in different combinations when the phase difference is large and small. Those error signals are used to drive a charge pump circuit 17 and then the loop time constant of the PLL circuit can be controlled corresponding to the phase difference.