| 摘要 |
PROBLEM TO BE SOLVED: To enable readjustment in the stable clock direction by detecting the direction of a phase drift of a sampling clock at regular or irregular intervals. SOLUTION: In a phase error comparison circuit 5, a clock phase shift circuit 8 compares clock phase error information obtained at the time of phase adjustment with that obtained at a normal time. When the clock phase error information obtained at the time of phase adjustment is smaller than that obtained at a normal time, an control instruction is outputted to the normal time clock phase adjusting circuit 7, respectively, if the clock phase shift circuit 8 shifts the phase in the leading direction, so that the phase of the normal time clock CLK is led by a minimum delay unit of a horizontal synchronous signal delay circuit 10, also, if the phase is shifted in the delaying direction, so that the phase of the normal time clock CLK is delayed by the minimum delay unit of a horizontal synchronous signal delay circuit 10.
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