| 摘要 |
PROBLEM TO BE SOLVED: To reduce jitters of reproducing clock signals without damaging follow-up ability, even if input signals fluctuate. SOLUTION: A PLL loop by phase comparison is constituted of a phase comparator 1 for detecting the phase difference between EFM signals 4, for which analog signals read from a disk are digitized and reproducing clock PCK signals 5, a loop filter 2 for filtering-processing the detected phase difference and a control oscillator 3 for controlling the frequency, based on the output of the loop filter 2 and outputting the PCK signals 5. Furthermore, a pulse width detection circuit 6 for counting the edge interval of the EFM signals 4 based on the PCK signals 5, discriminating whether the count value is within a prescribed range and controlling the operation stoppage of the phase comparator 1 corresponding to the result of the discrimination is provided. By this constitution, the gain of the phase comparator 1 is optimally adjusted. |
