| 摘要 |
PROBLEM TO BE SOLVED: To shorten the mean time of access from an instruction execution part and to improve the throughput by sending a read request from an instruction execution part to a small-capacity highspeed cache and a large-capacity cache at the same time and allowing respective processors to share and refer to the large-capacity cache. SOLUTION: The instruction execution part 100 sends a read request to an operand cache 108, an instruction cache 109, and a common cache 118 at the same time. When data to be read are present in the common cache 118, 16-byte data including the logical address of its operand are read out and transferred to the instruction execution part 100. The common cache 118 sends data including the corresponding data to the operand cache 108 when the data are present which are not used. When the data are not present which are stored in the operand cache 108, and 16-byte data that the instruction execution part 100 requires are transferred.
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