| 摘要 |
<p>PROBLEM TO BE SOLVED: To decrease the erasing speed of a fast discharging flash cell by generating a conditioning signal for removing many electric charges from the flash cell and applying the conditioning signal to the flash cell while the cell is in an unerased state. SOLUTION: Cells are all programmed, and it is considered that the cells are in the unerased state, i.e., a threshold voltage Vt is equal to Vp. Here, Vp is a target program state value. A series of conditioning signals (pulses) is applied to the cells of a memory array. Those signals remove many electric charges from the floating gates of the cells. The quantity of the electric charges is large enough to reduce a tunneling oxide electric field, but not enough to places the cells in an erased state. The erasure conditioning signals are applied to the control gates VCG and the sources and drains are still in a floating state. Positive potentials are established in both p-well and n-well areas until a p-substrate is grounded.</p> |
